View ICS85214I_291302.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FEATURES
* 5 differential HSTL compatible outputs * Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock inputs * CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL * CLK1 can accept the following input levels: LVCMOS or LVTTL * Output frequency up to 700MHz * Translates any single ended input signal to HSTL levels with resistor bias on nCLK0 input * Output skew: 40ps (maximum) * Part-to-part skew: 300ps (maximum) * Propagation delay: 1.8ns (maximum) * 3.3V core, 1.8V output operating supply * Lead-Free package fully RoHS compliant * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85214I is a low skew, high performance ICS 1-to-5 Differential-to-HSTL Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input accepts LVCMOS or LVTTL input levels. Guaranteed output and partto-par t skew characteristics make the ICS85214I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
nCLK_EN D Q LE CLK0 nCLK0 CLK1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO nCLK_EN VDD nc CLK1 CLK0 nCLK0 nc CLK_SEL GND
00 1
1
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
ICS85214I
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
85214AGI
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Type Description Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Power supply ground. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels. No connect. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pulldown Clock input. LVTTL / LVCMOS interface levels. Core supply pin. Synchronizing clock enable. When LOW, clock outputs follow clock input. Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Output supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13, 17 14 15 16 18 19 20 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 GND CLK_SEL nc nCLK0 CLK0 CLK1 VDD nCLK_EN VDDO Output Output Output Output Output Power Input Unused Input Input Input Power Input Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
85214AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Outputs Q0:Q4 Enabled nQ0:nQ4 Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs nCLK_EN 0
1 Disabled; LOW Disabled; HIGH After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 inputs as described in Table 3B.
Disabled
nCLK0 CLK0
Enabled
nCLK_EN
nQ0:nQ4 Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1 CLK0 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 X X nCLK0 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 X X CLK1 X X X X X X 0 1 Outputs Q0:Q4 LOW HIGH LOW HIGH HIGH LOW LOW HIGH nQ0:nQ4 HIGH LOW HIGH LOW LOW HIGH HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85214AGI
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol VDD VDDO IDD Parameter Input Power Supply Voltage Output Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 80 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current nCLK_EN, CLK_SEL CLK1 nCLK_EN, CLK_SEL CLK1 CLK1, CLK_SEL, nCLK_EN CLK1, CLK_SEL, nCLK_EN Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 Units V V V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0 CLK0 nCLK0 CLK0 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
85214AGI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Test Conditions Minimum 1 0 38% x (VOH - VOL) + VOL 0.6 Typical Maximum 1.4 0.4 60% x (VOH - VOL) + VOL 1.1 Units V V V V
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX VSWING Output Crossover Voltage
Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol fMAX tPD Parameter Output Frequency CLK0, nCLK0 CLK1 700MHz 1.0 Test Conditions Minimum Typical Maximum 700 300 1.8 40 300 20% to 80% 200 46 800 54 56 Units MHz MHZ ns ps ps ps % %
Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle CLK0, nCLK0
t sk(o) t sk(pp)
tR / tF odc
CLK1 266MHz 44 All parameters measured at fMAX unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85214AGI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V5% 1.8V0.2V
V DD
VDD VDDO
Qx
SCOPE
nCLK0 V CLK0
PP
HSTL
GND
nQx
Cross Points
V
CMR
GND
0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nQx PART 1 Qx nQy PART 2 Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
80%
CLK1 nQ0:nQ4 Q0:Q4 tPD
80% VSW I N G
Clock Outputs
20% tR tF
20%
OUTPUT RISE/FALL TIME
nCLK0 CLK0 nQ0:nQ4 Q0:Q4
tPD
nQ0:nQ4 Q0:Q4
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
PROPAGATION DELAY
85214AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
85214AGI
www.icst.com/products/hiperclocks.html
7
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
85214AGI
BY
www.icst.com/products/hiperclocks.html
8
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
near the power pin. For ICS85214I, the unused outputs can be left floating.
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS85214I. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located
Zo = 50 +
Zo = 50 R2 50 R1 50
-
U1
1.8V Zo = 50 Ohm
R12
1K
Zo = 50 Ohm C2 LVHSTL Driver R9 50 R10 50 0.1u
3.3V
11 12 13 14 15 16 17 18 19 1.8V 20 C1 0.1u
GND CLK_SEL nc nCLK CLK SCLK nc VDD nCLK_EN VDDO
nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0
10 9 8 7 6 5 4 3 2 1
Zo = 50 +
Zo = 50 R4 50 R3 50
-
ICS85214I ICS85214
Zo = 50 +
R11 1K Zo = 50 R8 50 R7 50 -
FIGURE 4. ICS85214I HSTL BUFFER SCHEMATIC EXAMPLE
85214AGI
www.icst.com/products/hiperclocks.html
9
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85214I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85214I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 227.2mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 227.2mW + 164mW = 391.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.391W * 66.6C/W = 111C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85214AGI
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT RL 50
FIGURE 5. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DDO_MAX
-V -V
) )
OH_MIN
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
OL_MAX
Pd_H = (1.0V/50) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
85214AGI
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85214I is: 674
85214AGI
www.icst.com/products/hiperclocks.html
12
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
13
85214AGI
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Marking ICS85214AGI ICS85214AGI ICS85214AGIL ICS85214AGIL Package 20 lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Count tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85214AGI ICS85214AGI ICS85214AGILF ICS85214AGILF
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85214AGI
www.icst.com/products/hiperclocks.html
14
REV. A JUNE 1, 2005
Integrated Circuit Systems, Inc.
ICS85214I
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Added Lead-Free marking in Ordering Information table. Date 6/1/05
Rev A
Table T9
Page 14
85214AGI
www.icst.com/products/hiperclocks.html
15
REV. A JUNE 1, 2005

▲Up To Search▲

Price & Availability of ICS85214I

	To Download ICS85214I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .